1. Field
This patent document relates to a data sense amplifier and a memory device including the same.
2. Description of the Related Art
Memory devices read and write data according to commands from a host. The basic unit for storing data is a memory cell. One memory cell includes one capacitor to store one-bit of data. In order to read the data stored in the capacitor and transmit the read data externally, the memory device has to accurately determine a logic level of the data stored in the memory cell. For this operation, memory devices include bit line sense amplifiers to amplify the data stored in the capacitor.
FIG. 1 is a diagram illustrating a bit line sense amplifier and peripheral components thereof.
Referring to FIG. 1, the bit line sense amplifier 110 may be coupled to a bit line BL and a bit fine bar BLB and memory cells MC1 and MC2 may be arranged at positions where the bit line BL and the bit line bar BLB intersect word lines WL1 and WL2, respectively. The memory cells MC1 and MC2 may include cell transistors T1 and T2 and cell capacitors C1 and C2, respectively.
An operation of the bit line sense amplifier 110 will be described as follows.
First, when the word line WL1 is activated to select the memory cell MC1, the cell transistor T1 is turned on, and charge sharing occurs between the bit line BL and the cell capacitor C1. The charge sharing may cause a potential difference between the bit line BL and the bit line bar BLB, and the bit line sense amplifier 110 may amplify the potential difference between the bit line BL and the bit line bar BLB. To amplify the potential, the bit line sense amplifier 110 may include cross-coupled inverters I1 and 12 which are driven through a pull-up power supply voltage RTO and a pull-down power supply voltage SB.
An equalizing unit 120 may equalize voltages of the bit line and bit line bar BL and BLB to a precharge voltage VBLP during a period in which an equalizing signal BLEQ is activated.
FIG. 2 is a diagram illustrating cell mats 210 and 220 and amplification units 230 to 250 of a memory device.
Referring to FIG. 2, each of the cell mats 210 and 220 may include a plurality of word lines WL, a plurality of bit lines BL and BLB, and a plurality of memory cells MC coupled between the word lines WL and the bit lines BL. Each of the amplification units 230 to 250 may include a plurality of bit line sense amplifiers BLSA. The bit line sense amplifiers BLSA of FIG. 2 may be configured in the same manner as the bit line sense amplifier of FIG. 1.
When the size of the cell mats 210 and 220 is increased or, particularly, when the length of the bit lines BL and BLB is increased, a larger number of memory cells MC may be integrated into the cell mats 210 and 220. However, when the length of the bit lines BL and BLB is increased, the capacitance of parasitic capacitors existing in the bit lines BL and BLB may also increase.
On the other hand, as the integration degree and capacity of the memory device are increased, the size of the cell capacitors is reduced. Thus, the capacitance of the cell capacitor decreases. That is, the quantity of charge that can be stored in each cell capacitor is reduced. When the capacitance of the cell capacitor decreases and the capacitance of the bit line increases, due to the high integration, a considerable amount of time may be required for increasing a potential difference between the bit lines BL and BLB to a predetermined level or more through charge sharing between the cell capacitor and the bit line, and the potential difference may be reduced. Accordingly, the number of memory cells integrated in the cell mat has to be decreased to reduce the length of the bit lines BL and BLB, thereby reducing the capacitance of the bit line.
FIG. 3 is a diagram for describing a phenomenon which occurs when the length of bit lines included in a cell mat is reduced.
In FIG. 3, the reference numeral ‘310’ indicates an example before the length of the bit lines is reduced, and the reference numeral ‘320’ indicates an example after the length of the bit lines is reduced. Suppose that the length of the bit lines in example 320 is reduced to a half of the length of the bit lines in example 310. Furthermore, suppose that the number of integrated memory cells is proportional to the lengths of the cell mats MT1 and MT2, that is, the lengths of the bit lines.
Referring to FIG. 3, the length of the cell mat MT2 in example 320 is reduced to half of the length of the cell mat MT1 in example 310. Thus, in example 320, the number of cell mats required for integrating the same number of memory cells as example 310 is two times larger than in example 310. FIG. 3 illustrates that two cell mats MT1 are provided in example 310 and four cell mats MT2 are provided example 320.
In order to amplify data of the cell mats MT1 or MT2, amplification units SA have to be arranged between the respective cell mats MT1 or MT2 and outside the cell mats MT1 or MT2. Thus, example 310 requires three amplification units SA, and example 320 requires five amplification units SA. Therefore, the area occupied by one amplification unit SA is equal in examples 310 and 320. Thus, in example 320, the area required for integrating the same number of memory cells is larger than in example 310.